What is Synchronous Counter : Working & Its Applications
- May 25, 2022
A counter can be defined as a device that is used to count a specific event based on the events that occurred. The main role of this counter within computers or a digital logic system is to count & store how many times a process or an event occurs based on a CLK signal. There are different types of counters like synchronous counter, asynchronous counter, synchronous decade, and asynchronous decade, synchronous up-down, and asynchronous up-down counter.
The most common type of a counter is a sequential logic circuit including a single CLK & several outputs. Here the outputs signify with binary or decimal numbers with binary code. Every CLK signal either enhances the number or reduces the number. This article discusses an overview of synchronous counter and its working with applications.
What is Synchronous Counter?
The synchronous counter can be defined as, a counter which uses a clock signal for transforming their transition. So, these counters mainly depend on the input of the clock to modify state values. In this counter, all flip flops (FFs) are associated with the same clock signal to activate simultaneously. An alternate name of this counter is a simultaneous counter where there is no ripple effect & propagation delay in these counters.
As compared to synchronous, asynchronous type designing is very simple but the asynchronous counter has a limitation of maximum operating frequency. To overcome this limitation, these counters are mainly designed by providing simultaneous clocking so, the output changes in synchronization through the input of the clock.
Synchronous Counter Circuit Diagram
The design & operation of the synchronous counter is explained below. The circuit diagram of the 3 bit synchronous counter is shown below and this circuit is designed with 2 AND logic gates, 3 J-K FFs & a CLK signal which is used to enable the Flip Flop.
Here, an active high signal is provided to the input terminal of flip flop A. Thus, it toggles at the reducing-edge of every CLK input. Similarly, the AND gate is provided to the flip flop -B where the output mainly depends on the previous FFs input & output B in this case. Once the AND gate switches ON then flip-flop B will toggle simply once the flip-flop A output is high.
In this way, the flip-flop C input will be the second AND gate’s output. So, flip-flop C toggles simply once the A2 logic gate is activated. When the output of the A1 logic gate and Flip Flop-B are high then the A2 logic gate will be activated.
Let us discusses the operation of a 3-bit synchronous counter. At the beginning of the circuit, the flip-flops are arranged at 0, then the three flip-flops outputs are will be zero like QCQBQA = 000. But at the dropping edge of the primary CLK signal, the flip-flop A output toggles from zero to one. So at flip-flops B & FF-C, there is no change will happen because these two FFs’ input terminals are 0 until the next CLK signal arrives.
Thus, on providing the first CLK signal, the outputs of the flip-flops will be QCQBQA = 001. Before applying the second clock signal, both the FFs like A & B inputs will be 1 due to the high gate A1 output. So, at the second CLK signal’s dropping edge, both the Flip Flops will toggle again. So this will change the FFA output from one to zero and FFB output from zero to one. Therefore, the output will be 010; both the logic gates like A1 & A2 will be turned OFF.
Once the third clock signal is applied, the flip-flop-A output will toggle and logic gates A1 & A1 will be turned ON, so the output will be 011. Once the fourth clock signal is applied then all the three FFs inputs will be high in the circuit. So the dropping edge of the fourth flip flop will toggle all the flip-flop outputs, thus changing QA & QB to 0 & QC to 1. Thus the overall o/p of this particular CLK signal will be 100, so logic gates A1 & A2 will be turned off.
Once the next CLK signal appears, then at the dropping edge of the fifth CLK signal, again the FF-A output will toggle from low to high. As a result, the outputs QCQBQA will be 10, so logic gates A1 & A2 will be activated.
Once the sixth CLK signal is applied then flip-flop A at its dropping edge toggles from 1 to 0. And also the input to flip-flop B is high therefore, its output toggles from 0 to 1. Thus, in this case, QCQBQA will be 110. Further, this process will continue & at the dropping edge of the 8th CLK signal, all the FFs outputs like QCQBQA will reset to 000.
In synchronous counters, it is significant that resetting all the FFs within the circuit occurs all at once. So the counter setting time is equal to every flip-flops propagation delay within the circuit. So, this counter can be controlled through a high-frequency CLK signal.
The truth table of the 3-bit synchronous counter is shown below based on the above explanation.
1st Falling Edge
|2nd Falling Edge||0||1||0||
|3rd Falling Edge||0||1||1||
4th Falling Edge
|5th Falling Edge||1||0||1||
|6th Falling Edge||
|7th Falling Edge||1||1||1||
|8th Falling Edge||0||0||0||
The timing diagram of the synchronous counter is shown below.
Synchronous Counter Types
In digital electronics, there are different types of synchronous counters available like binary counters, 4-bit synchronous UP, 4 bit synchronous DOWN, 4-bit synchronous UP or DOWN, BCD counter, Synchronous decade counter, 2 bit, 3 bit, loadable, Johnson counter, and ring counter. Some of them are discussed below.
A binary counter is an electronic circuit made with flip-flops where one flip-flop output is given as an input to the next flip-flop within a series. Based on the connection of flip flops (FFs) in the circuit, a binary counter can be used either synchronous or asynchronous. In a synchronous counter, all the FFs are activated through a similar CLK signal.
An asynchronous counter is known as a ripple counter. In this type of counter, the CLK signal is directly given to the first FF then it is transmitted with a propagation delay to another FF.
4- Bit Synchronous Up Counter
The designing of a 4- Bit synchronous up counter can be done like a 3-bit synchronous up counter but the difference is in the number of flip flops used. In this counter, four JK flip flops are used to design. The main reason to use this flip flop is, it toggles its condition if both the inputs are high based on the CLK signal.
An external CLK signal is given to all four flip-flops in parallel. This counter includes 16 output states where it counts from 0000 to 1111. As compared to 3-bit, the timing diagram of this counter & its operation is also the same.
4- Bit Synchronous Down Counter
The main function of this counter is to count the numbers in decreasing order. As compared to the up counter, the down counter is also the same but it must reduce its count. Thus, JK flip-flop inputs are connected toward the Q’ and the same external CLK signal is connected to four flip flops within the circuit.
Whenever this counter counts down the series, at first all the inputs of the FF will be in high condition because they have to count down the series. So, it will begin with 1111 & stop with 0000 like an up counter. In this type of counter, it should be noted that, if the front flip flop generates low logic at its output, then the previous flip flop will toggle simply.
2 bit Synchronous Counter
A 2-bit synchronous counter is designed through two reversible JK-Flip flops & two Feynman gates. Here, the Feynman gate is a CNOT or controlled- not gate which is used to copy a signal because in reversible logic circuits fan-out is not allowable. So this gate is used like a fan-out gate for copying a signal.
The CLK input is given to the Feynman gate where the output is allied to another gate like an input & also connected to reversible JK flip flop like CLK input.
Synchronous Up/Down Counter or Bidirectional Counter
The synchronous counter is designed to operate as an up/down counter using control signals because it is capable of counting in any direction so it is known as a bidirectional counter. In this counter, a JK flip-flop is used as a T flip-flop for bit storing.
For instance, a 3-bit bidirectional counter includes 8 possible output conditions. So based on the control input, it will count in any direction If this counter starts counting in an up direction, then the counting will be from 0 to 7. Once the control input is modified, then this counter will start counting in a downward direction from 7 to 0.
Here, the direction of counter operating will be decided by a control input. Once the control input is 1, and then it will stop the 2 & 4 AND gates and enable 1 & 3 gates. So at this condition, this counter will start counting in an upward direction.
Advantages & Disadvantages
The advantages & disadvantages of the synchronous counter include the following.
- As compared to asynchronous, it is simple to design
- It works simultaneously.
- No propagation delay is linked with it.
- Count series is controlled through logic gates,
- Faster operation
The main disadvantage of a synchronous counter is, it needs a lot of additional logic to execute.
- All flip flops are driven through a single or common CLK signal
- They need large components & circuitry.
- This counter uses a complex logic circuit & the increasing number of states.
The applications of synchronous counter include the following.
- Motion control of the machine
- Motor RPM counter
- Rotating Shaft Encoders
- Pulse generators
- Digital clock
- Alarm systems
- Digital Watch
(1). Which FF is used in synchronous counter?
The synchronous counter uses edge-triggered FFs for changing the conditions on either the rising edge (positive-edge) or the falling edge (negative-edge) of the CLK signal on the control input.
(2). What are synchronous devices?
Devices that communicate synchronously with each other through a separate clocking channel are known as synchronous devices.
(3). How many states will there be in a 4-bit synchronous counter?
In a 4-bit synchronous counter, the total number of states is 2^4 = 16 states.
(4). What is a 3 bit synchronous down counter?
The 3-bit synchronous down counter is designed with an AND gate and three T flip-flops. These three flip-flops are negative edge triggered & the outputs of these FFs will change their effect synchronously. Here, the ‘T’ inputs of all the flip-flops are 1, Q0′, and ‘ Q1′Q0′ correspondingly
Thus, this is all about an overview of the synchronous counter which can be made with D-type or Toggle flip-flops. As compared to asynchronous, these are very simple to design. As the name suggests, the CLK input of all the flip-flops is all clocked mutually with the same CLK signal so all output states will change or switch simultaneously. Here is a question for you, what is a synchronous decade counter?