What are the properties of SiC crystals

Silicon carbide (SiC) is superior to conventional silicon in the design of high-power electronic devices, and developers have more knowledge of the physical properties of SiC materials and also the performance of this high-performance compound semiconductor is widely adopted, but it is still a challenge to control the defect density of the crystal in the application.

The remaining question is whether the manufacturing cost of SiC devices will enable device products to compete with silicon power devices in system applications. The properties of SiC allow for the design of power devices with smaller areas, or in other words, devices that can be designed for greater current densities. This advantage offers the opportunity to fill the wafer with a large number of transistors compared to traditional silicon power device designs.

A small increase in the number of devices on the wafer, or a small reduction in the core area of the SiC device required to achieve device manufacturing cost parity with the equivalent specified silicon device. The properties of SiC, particularly its thermal conductivity, allow device design strategies to achieve a 2-fold reduction in core area. This calculation shows that for Si and SiC, there may be a significant difference in price between wafers of the same size, but the cost to fabricate the devices is comparable.

Exploiting the high voltage and thermal conductivity properties of SiC compared to silicon is critical to the successful implementation of device and system designs. In order to achieve successful device performance, it is also important to understand the other characteristics of SiC wafers.


SiC wafers are transparent, which can lead to some difficulties in using lithography, automated defect detection and automated wafer handling. Automatic defect detection may misidentify features below the surface as surface defects. In wafer handling, sensors set up for opaque materials may respond incorrectly, leading to wafer breakage during the loading/unloading process.

Dopant doping.

The injection and activation of dopant atoms in SiC is more challenging than doping in silicon. The diffusion of dopants is very small compared to silicon. In SiC, injection activation requires temperatures in excess of 1500°C, during which the wafer surface must be kept free of roughness. The activation efficiency may be lower than that of silicon and the total activation varies with the total dopant concentration.

Substrate resistivity.

SiC substrates have a higher resistivity than silicon substrates. Because of the smaller epitaxial thickness used in SiC designs compared to silicon, SiC substrates can provide a margin for the series resistance of the device. The formation of ohmic contacts on SiC wafers typically requires high temperature annealing (T " 800°C). Since annealing temperatures can be detrimental to subsequent device processes, this step must be performed early in the device manufacturing process. Process optimization is critical to ensure that series resistance effects caused by ohmic contacts are minimized and that optimal low forward voltage drop performance is achieved in SiC diodes and metal oxide semiconductor field effect transistors (MOSFETs).


The most critical defects associated with SiC devices are the polycrystalline surface defects that form on the wafer surface during epitaxy. These fatal defects can be easily detected by automated spectroscopy techniques. Defective surface protrusions can lead to the formation of large bad spots in the photoresist layer and cause manufacturing failures in areas of the wafer away from the defect. Inspection of the photoresist is an important process step in identifying potential manufacturing problems. Other defects may also be present that may limit the performance of the device. Minor photodamage from the polishing process can lead to shallow linear defects on the epitaxial surface that will be repaired in the metallization step. These defects may cause the device to have some problem spots in the area below the gate or in the edge termination area.

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