Designing of 3 Line to 8 Line Decoder and Demultiplexer
- Frank
- Jun 02, 2022
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The conversion of binary to decimal can be done using a device namely a decoder. This device is one kind of combinational logic circuit that uses the n-input lines to generate 2n output lines. Here, the output of this device might be below 2n lines. There are different kinds of binary decoders which include multiple inputs as well as multiple outputs. Some kinds of decoders include one or more enable inputs along with the data inputs. Whenever the enable input is disabled then all the outputs will be inactivated. Based on its function, a binary decoder changes the data from n-input signals to 2n output signals. In some kinds of decoders, they have below 2n output lines. So in that situation, a minimum of one output prototype may be repeated for various input values. There are two kinds of higher-order decoders like 3 Line to 8 Line Decoder & 4 Line to 16 Line Decoder. This article discusses an overview of 3 Line to 8 Line Decoder.
What is a Decoder?
A decoder is a combinational logic circuit that is used to change the code into a set of signals. It is the reverse process of an encoder. A decoder circuit takes multiple inputs and gives multiple outputs. A decoder circuit takes binary data of ‘n’ inputs into ‘2^n’ unique output. In addition to input pins, the decoder has a enable pin. This enables the pin when negated, to make the circuit inactive. in this article, we discuss 3 to 8 line Decoder and demultiplexer.
The below is the truth table for a simple 1 to 2 line decoder where A is the input and D0 and D1 are the outputs.
The circuit shows the 1 to 2 decoder logic.
A demultiplexer is a device that takes a single input and gives one of the several output lines. A demultiplexer takes one single input data and then selects any one of the single output lines one at a time. It is the reverse process of a multiplexer. It is also called as a DEMUX or a data distributor. A DEMUX converts the input serial data line into output parallel data. A DEMUX gives ‘2n’ outputs for ‘n’ selection lines with a single input.
DEMUX is used when the circuit wishes to send the data signal to one of the many devices. A decoder is used to select among many devices whereas a demultiplexer is used to send the signal to many devices.
The below is the truth table for 1 to 2 demultiplexer with “I” as input data, D0 and D1 are the output data line and A is the selection line.
The circuit shows the 1 to 2 demultiplexer schematic.
Why do we need a Decoder?
The main function of a decoder is to change a code into a set of signals because it is opposite to an encoder, but the designing decoders is simple. The main difference between a decoder and a demultiplexer is a combinational circuit that is used to allow only one input as well as direct it into one of the outputs, whereas a decoder allows several inputs and generates the decoded output.
3 Line to 8 Line Decoder Designing Steps
Here, 3 line to 8 line decoder is a higher-order decoder that is designed with two low order decoders like 2 line to 4 line decoders. Before going to implement this decoder we have designed a 2 line to 4 line decoder.
2 Line to 4 Line Decoder
This 2 line to 4 line decoder includes two inputs like A0 & A1 & 4 outputs like Y0 to Y4. The block diagram of this decoder is shown below.
When the inputs and enable are 1 then the output will be 1. Here is the truth table of 2 to 4 decoder.
E |
A1 | A0 | Y3 | Y2 | Y1 |
Y0 |
0 |
x | x | 0 | 0 | 0 | 0 |
1 |
0 | 0 | 0 | 0 | 0 | 1 |
1 |
0 | 1 | 0 | 0 | 1 |
0 |
1 | 1 | 0 | 0 | 1 | 0 |
0 |
1 | 1 | 1 | 1 | 0 | 0 |
0 |
The boolean expression for every output is
Y3 = E. A1. A0
Y2 = E. A1. A0′
Y1 = E. A1′. A0
Y0 = E. A1′. A0′
Every output of this decoder includes one product term. So the four product terms can be implemented through 4 AND gates where each gate includes 3 inputs as well as 2 inverters. The 2 to 4 decoder logic diagram is shown below. Thus, this decoder’s output is nothing but the minterms of inputs and enable is equivalent to 1. If enable is zero, afterward all the decoder’s outputs will be equivalent to zero. Likewise, 3 line to 8 line decoder generates eight minterms for 3 input variables of A0, A1 & A2.
3 Line to 8 Line Decoder Implementation
The implementation of this 3 line to 8 line decoder can be done using two 2 lines to 4 line decoders. We have discussed above that 2 to 4 line decoder includes two inputs and four outputs. So, in 3 lines to 8 line decoder, it includes three inputs like A2, A1 & A0 and 8 outputs from Y7 – Y0.
The following formula is used to implementation of higher-order decoders with the help of low order decoders
The number of lower-order decoders required is m2/m1
Where,
The number of o/ps for the lower-order decoder is ‘m1’
The number of o/ps for higher-order decoder is ‘m2’
For instance, when m1 = 4 & m2 = 8, then substitute these values in the above equation. We can get the required no. of decoders are 2. So, for implementing a single 3 to 8 decoder, we need two 2 lines to 4 line decoders. Here, the block diagram is shown below by using two 2 to 4 decoders.
The parallel inputs like A2, A1 & A0 are given to 3 lines to 8 line decoder. Here the compliment of A3 is given to enable the pin of the decoder to obtain the outputs like Y7 to Y0. These outputs are lower 8 minterms. In the above decoder, the A3 input is connected to enable the pin to obtain the outputs from Y15 – Y8. So, these outputs are the higher 8 minterms.
3 Line to 8 Line Decoder using Logic Gates
In 3 to 8 line decoder, it includes three inputs and eight outputs. Here the inputs are represented through A, B & C whereas the outputs are represented through D0, D1, D2…D7.
The selection of 8 outputs can be done based on the three inputs. So, the truth table of this 3 line to 8 line decoder is shown below. From the following truth table, we can observe that simply one of 8 outputs from DO – D7 can be selected depending on 3 select inputs.
A | B | C | D0 | D1 | D2 | D3 | D4 | D5 | D6 |
D7 |
0 |
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
0 |
0 |
0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
0 |
0 |
1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
0 |
1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
From the above truth table of 3 lines to 8 line decoder, the logic expression can be defined as
D0 = A’B’C’
D1= A’B’C
D2 = A’BC’
D3 = A’BC
D4 = AB’C’
D5= AB’C
D6 = ABC’
D7 = ABC
From the above Boolean expressions, the implementation of 3 to 8 decoder circuit can be done with the help of three NOT gates & 8-three input AND gates.
In the above circuit, the three inputs can be decoded into 8 outputs, where every output represents one of the midterms of the three input variables.
The 3 inverters in the above logic circuit will provide the complement of the inputs & each one of the AND gates will generate one of the midterms.
This kind of decoder mainly used to decode any 3-bit code & generates eight outputs, equivalent to 8 different combinations for the input code.
This decoder is also known as a binary to octal decoder because the inputs of this decoder represent three-bit binary numbers whereas the outputs represent the 8 digits within the octal number system.
3 Line to 8 Line Decoder Block Diagram
This decoder circuit gives 8 logic outputs for 3 inputs and has a enable pin. The circuit is designed with AND and NAND logic gates. It takes 3 binary inputs and activates one of the eight outputs. 3 to 8 line decoder circuit is also called a binary to an octal decoder.
The decoder circuit works only when the Enable pin (E) is high. S0, S1 and S2 are three different inputs and D0, D1, D2, D3. D4. D5. D6. D7 are the eight outputs. The logic diagram of the 3 to 8 line decoder is shown below.
3 to 8 Line Decoder and Truth Table
The below table gives the truth table of 3 to 8 line decoder.
S0 | S1 | S2 | E | D0 | D1 | D2 | D3
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